custom-hdl/ ├── external/ │ └── slang/ # Slang submodule (Verilog parser) ├── src/ │ ├── main.cpp # Entry point │ ├── ir_builder.cpp # AST to IR transformation │ └── ir_builder.h # IR node definitions ...
This project is a complete System-on-Chip (SoC) verification environment built using SystemVerilog and UVM. Instead of verifying protocols in isolation, this project verifies a Peripheral Subsystem.
The Dabao open-source hardware board features a Boachip-1x RISC-V MCU, whose RTL Verilog files are also open, and is IRIS inspectable.
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